Digital-to-analog converters (DACs) are widely used in many applications, including telecomm. Current sources that are switched by the digital bits being converted are common. The switched current generates an analog voltage when passed through a resistor. However, these current-source DACs consume much power.
DACs are sometimes constructed using switched capacitors rather than current sources. The digital bits switch a voltage supply to capacitors with binary-increasing weights. Charge is transferred from these capacitors to an integrating capacitor and amplified by an op amp.
Since charge is simply redistributed with the switched-capacitor DAC, power consumption is significantly reduced compared with current-source DACs. However, precise clocks are needed to time the transfer of charge, and glitches on the output can occur.
Switched-Capacitor DAC--FIG. 1
FIG. 1 is a diagram of a prior-art switched-capacitor DAC. A two-phase non-overlapping clock is used having phases PH1 and PH2. During PH2, switch 12 closes, shorting the output of op amp 14 to its inverting input. This auto-zeros op amp 14 to its equilibrium point at ground. Summing node 10 is actively driven to ground by the output of op amp 14, discharging all capacitors connected to summing node 10. Integrating capacitor 19 is connected to ground by switch 16, discharging integrating capacitor 19, which has a capacitance of 32C.
Switched capacitors 20, 22, 24, 26, 28 have binary-increasing capacitances C, 2C, 4C, 8C, 16C, where C is the capacitance of the smallest capacitor 20. The backside of switched capacitors 20, 22, 24, 26, 28 are connected to either Vref or ground GND by switches 18, depending on the binary bits. For example, the binary word 01001 connects capacitors 20 and 26 to the higher voltage Vref, since bits 0 and 3 are high. Capacitors 22, 24, 28 are connected to ground, since bits 1, 2, 4 are low.
When connected to Vref, the charge across a capacitor is Vref multiplied by its capacitance. When connected to ground, the charge across a capacitor is zero.
Phase PH2 is known as the precharge phase, since all capacitors are actively charged by being connected to nodes actively driven to set voltages Vref, or ground. Any input-offset or bias in op amp 14 is adjusted for by the auto-zeroing of switch 12.
In the next phase, PH1, switch 12 opens, disconnecting the input and output of op amp 14. Switch 16 connects the back side of integrating capacitor 19 to ground. The total charge is summed and a new voltage appears at the input node of op amp 14. The feedback then forces the voltage at the output of op amp 14 to increase. By increasing the voltage at the output of op amp 14, the voltage at summing node 10 is held to ground.
Switches 18 connect the back sides of capacitors 20, 22, 24, 26, 28 ground during PH1, and to ground or Vref during PH2. This causes charge to be removed from or added to summing node 10. When a switch 18 had connected a capacitor high to Vref during PH2, the switch to a lower voltage during PH1 pulls positive charge from summing node 10. When a switch 18 had connected a capacitor low to ground during PH2, the switch to a higher voltage during PH1 injects positive charge to summing node 10. The amount of charge depends on the capacitance of each capacitors 20, 22, 24, 26, 28 switched high or low.
Since integrating capacitor 19 has a capacitance of 32C, while the total capacitance of capacitors 20, 22, 24, 26, 28 is 31C, summing node 10 is always pulled lower in voltage,. The amount of voltage drop on summing node 10 depends on which capacitors 20, 22, 24, 26, 28 were switched high or low during PH2. The output voltage Vout=(Vref/31C)(D4*16C+D3*8C+D2*4C+D1*2C+D0*C).
When more capacitors 20, 22, 24, 26, 28 were switched high, a larger voltage drop occurs on summing node 10, and the higher the voltage output by op amp 14. Thus a digital value applied to switches 12 during PH2 creates a proportional analog voltage at the output of op amp 14 during the following phase PH1.
Capacitor Mis-Match
One problem with the prior-art switched-capacitor DACs is that of capacitor mis-match. The switched capacitors are typically constructed from polysilicon-oxide-polysilicon layers. Process variations such as layer-misalignment or etch variations can cause variations in capacitance values of different capacitors. These variations may be only a few percent of the total capacitance. However, a 5 % variance of largest capacitor 28 is 16C*0.05 or 0.8C, about the size (1.0C) of the smallest capacitor 20. For larger DACs, such as a 10-bit DAC, the largest capacitor is C*2.sup.10 or 1024C, and a 5% variation is 51C, many times larger than the smallest capacitors.
It is desired to reduce the effect of these variations in capacitor values, especially for the larger capacitors. What is desired is a switched-capacitor DAC that reduces the effect of capacitance-value error. A multi-bit DAC using charge-redistribution is desired that smoothes out variances of capacitances in the larger capacitors. A low-power DAC with reduced error is desirable.